The present invention relates generally to the fabrication of planar lightwave circuits. More particularly, the present invention relates to a method and system for a high-density plasma deposition process for fabricating a top clad for an arrayed waveguide grating planar lightwave circuit.
Planar lightwave circuits (PLCs) comprise fundamental building blocks for the modern fiber optic communications infrastructure. Planar lightwave circuits are generally devices configured to transmit light in a manner analogous to the transmission of electrical currents in printed circuit boards and integrated circuit devices. Examples include arrayed waveguide grating devices, integrated wavelength multiplexers/demultiplexers, optical switches, optical modulators, wavelength-independent optical couplers, and the like.
PLCs generally involve the provisioning of a series of embedded optical waveguides upon a semiconductor substrate, with the optical waveguides fabricated from a silica glass. Planar lightwave circuits are constructed using the advanced tools and technologies developed by the semiconductor industry. Modern semiconductor electronics fabrication technology can aggressively address the increasing need for integration is currently being used to make PLCs. By using manufacturing techniques closely related to those employed for silicon integrated circuits, a variety of optical elements can be placed and interconnected on the surface of a silicon wafer or similar substrate. This technology has only recently emerged and is advancing rapidly with leverage from the more mature tools of the semiconductor-processing industry.
PLCs are constructed with a number of waveguides precisely fabricated and laid out across a silicon wafer. A conventional optical waveguide comprises an undoped silica bottom clad layer, with at least one waveguide core formed thereon, and a cladding layer covering the waveguide core, wherein a certain amount of at least one dopant is added to both the waveguide core and the cladding layer so that the refractive index of the waveguide core is higher than that of the cladding layer. Fabrication of conventional optical waveguides involves the formation of an undoped silica layer as the bottom clad (BC), usually grown by thermal oxidation upon a silicon semiconductor wafer. The core layer is a doped silica layer, which is deposited by either plasma-enhanced chemical vapor deposition (PECVD) or flame hydrolysis deposition (FHD). An annealing procedure then is applied to this core layer (heated above 1000 C.) not only to expel the undesired chemical substance such as the radicals with bonded hydrogen but also to reduce the inhomogenities of refractive index within the core layer. The waveguide pattern is defined by photolithography on the core layer, and reactive ion etch (RIE) is used to remove the excess doped silica to form waveguide core. A SiO2 cladding layer is then formed through a subsequent deposition process. Finally, the wafer is cut into multiple planar lightwave circuit dies and packaged according to their particular applications.
Prior art FIG. 1 shows a cross-section view of a conventional planar optical waveguide. As depicted in FIG. 1, the planar optical waveguide includes three doped SiO2 glass cores 10a-10c formed over a SiO2 silica bottom clad 12. A BPSG top cladding layer 11 covers both the cores 10a-c and the bottom clad 12. As described above, the refractive index of the cores 10a-c is higher than that of the top cladding layer 11 and the bottom clad 12. Consequently, optical signals are confined axially within cores 10a-c and propagate lengthwise through cores 10a-c. The cores 10a-c are typically doped with Germanium to increase their index of refraction.
Arrayed waveguide grating planar lightwave circuits are one of the most precisely manufactured PLCs. Arrayed waveguide grating devices are used to implement multiplexing or demultiplexing functions within a fiber-optic network. A typical arrayed waveguide grating device is configured for multiplexing or demultiplexing, for example, 16 channels with a separation of 100 gigahertz between the channels. Arrayed waveguide grating devices having 40 channels spaced at 50 gigahertz are commercially available, and even more advanced devices having 128 channels spaced at 25 gigahertz have been demonstrated. Such advanced arrayed waveguide grating devices have enabled the provisioning of dense wave division multiplexing (DWDM) fiber-optic networks, which are increasingly being relied upon to handle the geometrically expanding demand for data transfer bandwidth.
The performance of such advanced arrayed waveguide grating devices (e.g., 40 channels or more) is critically dependent upon the performance of the semiconductor manufacturing technologies used to fabricate them. For example, a 128 channel arrayed waveguide grating device will have at least 128 precisely defined optical waveguides fabricated therein. Small defects, anomalies, imperfections, or the like, have very significant impacts upon the performance of an arrayed waveguide grating device. Any such defect, for example, can directly affect the channel isolation of any of the waveguides within the affected area of the defect, cause signal loss from waveguides within the affected area, or the like. Hence, to maintain acceptable yields while providing the required performance, it becomes extremely important to ensure the fabrication of the optical waveguides of the arrayed waveguide grating devices are as precise and deterministic as possible.
Prior art FIGS. 2A through 2C depict a top clad deposition process wherein three waveguide cores 21-23 are covered during a deposition process to form the top clad (e.g., top cladding layer 11 as shown in FIG. 1). A well known problem with the fabrication of an arrayed waveguide grating devices is the gap fill of high aspect ratio areas between optical waveguide cores during top clad deposition. FIG. 2A shows three cores 21-23 out of the numerous waveguide cores comprising, for example, a 16 channel arrayed waveguide grating device. FIG. 2B shows three waveguides 21-23 at an intermediate step of the top clad deposition process. As shown in FIG. 2B, the gaps between cores 21-23 have been partially filled by the top clad layer 25. Subsequently, as shown in FIG. 2C, when the top clad deposition process is complete, the gaps between cores 21-23 are completely filled and the top clad layer 26 is completely flat and without voids.
Prior art FIG. 3 shows the problems which occur during a top clad deposition process of a highly integrated PLC device. FIG. 3 shows three cores 31-33 which are more closely spaced with respect to waveguides 21-23 of FIG. 2. As is well known, the closely spaced cores 33-31 present high aspect ratio gaps between them which must be filled during the top clad deposition process. The high aspect ratio of the gaps causes micro voids 41 and 42 to form as top clad layer 37 is deposited. The voids 41-42 are serious defects which significantly affect the performance of the waveguides comprising cores 31-33. In a case where the defects are not so significant as to create voids, there may be low density areas within the gaps instead of voids. Crystallization will develop in these low density areas. The areas of local crystallization also adversely affects the performance of the waveguides. Typical prior art top clad deposition processes (e.g., PECVD) can only fill gaps larger than 2 microns (e.g., at an aspect ratio of 3) or larger while ensuring the absence of voids or local crystallization problems.
One solution to this problem is to utilize a very gradual top clad xe2x80x9cbuildupxe2x80x9d process, wherein a number of deposition and anneal cycles are used to gradually buildup the thickness of the top clad layer. Successive thin top clad layers (e.g., typically 4 layers at minimum) are deposited and annealed in an attempt to avoid the formation of voids. While this solution is somewhat effective in filling high aspect ratio gaps, the large number of deposition and anneal cycles greatly decreases the throughput of the fabrication line.
Thus what is needed is a solution that can effectively fill high aspect ratio gaps between waveguide cores of an arrayed waveguide grating PLC device. What is needed is a solution that can fill high aspect ratio gaps without adding an excessive amount of time to the overall device fabrication process. What is further required is a solution that can fill high aspect ratio gaps while ensuring no voids or crystallization problems occur. The present invention provides a novel solution to the above requirements.
The present invention is a high-density plasma deposition process for fabricating a top clad that can effectively fill high aspect ratio gaps between waveguide cores of an arrayed waveguide grating planar lightwave circuit device. The present invention provides a solution that can fill high aspect ratio gaps while reducing the overall device fabrication process time. Additionally, the present invention provides a solution that can fill high aspect ratio gaps while ensuring no voids or crystallization problems occur.
In one embodiment, the present invention is implemented as a high-density plasma (HDP) deposition process for fabricating a top clad for an arrayed waveguide grating PLC. The HDP deposition process is optimized for performing high aspect ratio gap fill during PLC top clad deposition. During fabrication of the arrayed waveguide grating device, a plurality of waveguide cores are formed on a bottom clad, the waveguide cores having a plurality of gaps there between. The refractive index of the waveguide cores are controlled by using a dopant to be higher than the refractive index of the cladding layer. A cladding layer is formed over the waveguide cores and the bottom clad using an HDP deposition process. The HDP deposition process effectively fills the gaps between the cores. The gaps between the waveguide cores can be smaller than 2 microns. The aspect ratio of the gaps between the waveguide cores can be greater than 3. A one step HDP deposition process can fill the gaps completely. An anneal process is performed on the cladding layer after the HDP deposition process. The HDP deposition process provides a very high purity USG (undoped silica glass) layer having a uniform refractive index. Subsequently, an overlying layer of doped silica glass (e.g., BPSG) can be deposited over the cladding layer using a conventional plasma enhanced chemical vapor deposition (PECVD) process in a one step deposition and anneal cycle to obtain the desired thickness.
The process of the present invention enhances device yield due to the fact that the HDP deposition process can fill high aspect ratio gaps while greatly reducing the number of deposition and anneal cycles, and thus time, of the overall device fabrication process. Additionally, the HDP deposition process solves crystallization problems in the gap areas experienced in the prior art.
In another embodiment, the HDP deposition process is used to deposit a BPSG top clad instead of a USG top clad to reduce the top clad stress. Boron and phosphene is added during the HDP deposition to adjust the CTE (coefficient of thermal expansion) of the top clad (e.g., the resulting CTE of the top clad after anneal) to match the CTE of the silicon substrate. This greatly reduces PDW effects within the PLC device.